Capability brief
ASICs, integration, and detector electronics we stand behind
This is the layer where “it works on the eval board” either becomes a product or fails thermally, mechanically, and statistically. We define multichannel readout IC requirements, plan wirebond and hybrid attach paths, and close the loop with FPGA, firmware, and calibration so pixels behave as a system.
Multichannel readout ASICs
We translate detector physics into channel counts, peaking times, noise floors, power per channel, and multiplexing choices that survive yield and packaging reality.
Bench bring-up, trim strategies, and correlation with TCAD or empirical sensor data are part of the same engagement—not a handoff to another vendor.
Wirebond, hybridization, and packaging
Pixelated Cd(Zn)Te and related sensors demand disciplined bump, wirebond, and underfill planning: loop profiles, pull strength, thermal expansion, and rework risk all feed back into ASIC pad maps and mechanical fixtures.
We plan system-in-package and miniaturization steps when your program targets aerospace, portable instruments, or dense channel tiling.
Detector contacts: AZO, lifetime, and charge collection
Electrical contact to wide-bandgap semiconductor detectors is rarely “just metallization.” We apply aluminum-doped zinc oxide (AZO) contact strategies intended to improve charge collection efficiency and extend operational life versus legacy contact stacks that can degrade under bias and radiation stress.
Those improvements show up downstream as stable leakage, predictable spectroscopic resolution, and fewer field failures attributed to contact drift.
Patents and protectable differentiation
Our intellectual property spans detector interfacing, readout architectures, and integration methods that survive harsh environments. We engage under NDA with qualified partners when detailed claim mapping is required for your freedom-to-operate or licensing discussions.
DOE Phase I and national-lab-class problems
We have also been awarded Department of Energy Phase I funding—alignment with missions that demand radiation-hard sensing, credible metrology, and transfer paths from R&D toward deployable hardware.
FPGA, DAQ, and real-time digital
ASIC outputs meet the world through FPGA fabric: triggers, time stamping, PCIe or Ethernet offload, and embedded control. We implement DSP chains that preserve the analog front-end’s intent instead of smearing it with naive filtering.